The present application relates generally to semiconductor devices, and more specifically to vertical field effect transistors (VFETs) and their methods of production.
Vertical fin FETs are devices where the source-drain current flows from a source region to a drain region through a channel region of a semiconductor fin in a direction normal to a substrate surface. An advantage of the vertical FET is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. In vertical fin field effect transistor (FinFET) devices, the fin defines the transistor channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin.
The vertical fin field effect transistor structure can be used to form a wide variety of devices, including long channel and short channel devices. Fins having different heights may be used to locally define the channel length of different devices on the same substrate. However, notwithstanding recent developments, it remains a challenge to form semiconductor fins on the same substrate having different fin heights (and different channel lengths), and to subsequently form top source/drain junctions that are aligned to respective ones of the fins.